Many electronic components within integrated circuits are sensitive to electrostatic discharge (ESD) and other forms of voltage spikes. An ESD event is a sudden flow of electricity between two or more objects. The electrical flow can be initiated in several ways, such as electrical contact, a short, or a dielectric breakdown. The static electricity developed by walking across a carpet can be enough to damage some devices, where static electricity often has very high voltage. In many cases, an ESD event will damage or destroy one or more electronic components in an integrated circuit, and ESD events are common.
Various techniques are used to prevent electronic component damage due to ESD events. For example, manufacturers may utilize electrostatic protective areas that are essentially free of static electricity. This can involve several measures, such as avoiding the use of highly charging materials, grounding objects and/or workers, and controlling humidity. Many integrated circuits are transported in special containers that are designed to prevent damage from ESD events, such as anti-static bags that include partially conductive plastics or other conductive materials. However, it is difficult or impossible to prevent ESD events from damaging integrated circuits while in use by employing special handling measures. For example, an integrated circuit included in a motor vehicle is exposed to many different conditions, so prevention of ESD events is difficult. ESD events for many handheld devices, portable devices, and even fixed electronic devices are common, and protective measures may be prohibitive. Some integrated circuits include design features to protect electronic components, but such protection has limits.
To protect the integrated circuits from ESD events while in use, many integrated circuits are provided with an ESD circuit, where the ESD circuit includes an ESD transistor that is designed to act during an ESD event. More particularly, ESD circuits are generally designed to remain quiescent during normal operation of the integrated circuit and to turn on during an ESD event. A typical ESD device has a trigger voltage (Vt) that is higher than operating voltage (Vo) of the integrated circuit, with the ESD device remaining in the quiescent state until applied voltage reaches or exceeds Vt. Once Vt is reached or exceeded for the ESD device, the ESD device becomes activated and the current increases to a holding point, which is demarcated by a peak decrease in voltage versus current increase. During the ESD event, once the holding point is exceeded, current continues to increase along with voltage until a failure point is reached, as demarcated by a sharp decrease in voltage with further increase in current. The current and voltage at the failure point is often designated as It2 and Vt2, respectively.
To configure ESD devices for particular integrated circuits, the ESD devices are designed according to desired specifications for Vt, Vh, Vt2, and It2. However, ESD devices that are configured for lower Vh are often vulnerable to latch-up failure or short circuit such that higher Vh is often desired for certain integrated circuits. However, Vh is generally correlated to It2, with increasing Vh generally leading to undesirably lower It2. Thus, typical ESD device configurations present a trade-off between established Vh and It2 for the ESD devices.
Accordingly, it is desirable to provide integrated circuits including ESD devices that exhibit a minimal change in failure current (It2) even when configured to have a higher holding voltage. In addition, it is desirable to provide methods of forming the integrated circuits that include the ESD devices. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.